pronounced "see-moss"), also known as complementary-symmetry metal–oxide–semiconductor
), is a type of metal–oxide–semiconductor field-effect transistor
(MOSFET) fabrication process
that uses complementary and symmetrical pairs of p-type
MOSFETs for logic functions.
CMOS technology is used for constructing integrated circuit
(IC) chips, including microprocessors
, memory chips
(including CMOS BIOS
), and other digital logic
circuits. CMOS technology is also used for analog circuits
such as image sensors
), data converters
, RF circuits
), and highly integrated transceivers
for many types of communication.
Two important characteristics of CMOS devices are high noise immunity
and low static power consumption
Since one transistor
of the MOSFET pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat
as other forms of logic, like NMOS logic
or transistor–transistor logic
(TTL), which normally have some standing current even when not changing state. These characteristics allow CMOS to integrate a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most widely used technology to be implemented in VLSI chips.
"CMOS" refers to both a particular style of digital circuitry design and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power
than logic families
with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes.
CMOS logic consumes over 7 times less power than NMOS logic
and about 100,000 times less power than bipolar transistor-transistor logic
CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistor
(MOSFETs) to implement logic gates
and other digital circuits. Although CMOS logic can be implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits composed of up to billions of transistors of both types, on a rectangular piece of silicon
of between 10 and 400 mm2
CMOS always uses all enhancement-mode
MOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).
The principle of complementary symmetry was first introduced by George Sziklai
in 1953 who then discussed several complementary bipolar circuits. Paul Weimer
, also at RCA
, invented in 1962 TFT
complementary circuits, a close relative of CMOS. He invented complementary flip-flop
and inverter circuits, but did no work in a more complex complementary logic. He was the first person able to put p-channel and n-channel TFTs in a circuit on the same substrate. Three years earlier, John T. Wallmark
and Sanford M. Marcus published a variety of complex logic functions implemented as integrated circuits using JFETs
, including complementary memory circuits. Frank Wanlass was familiar with work done by Weimer at RCA.
A new type of MOSFET logic combining both the PMOS and NMOS processes was developed, called complementary MOS (CMOS), by Chih-Tang Sah and Frank Wanlass
at Fairchild. In February 1963, they published the invention in a research paper
Wanlass later filed US patent 3,356,858
for CMOS circuitry in June 1963, and it was granted in 1967. In both the research paper and the patent
, the fabrication of CMOS devices was outlined, on the basis of thermal oxidation
of a silicon substrate to yield a layer of silicon dioxide
located between the drain contact and the source contact.
CMOS technology was initially overlooked by the American semiconductor industry
in favour of NMOS, which was more powerful at the time. However, CMOS was quickly adopted and further advanced by Japanese semiconductor manufacturers due to its low power consumption, leading to the rise of the Japanese semiconductor industry. Toshiba
developed C²MOS (Clocked CMOS), a circuit technology with lower power consumption
and faster operating speed than ordinary CMOS, in 1969. Toshiba used its C²MOS technology to develop a large-scale integration
(LSI) chip for Sharp
's Elsi Mini LED pocket calculator
, developed in 1971 and released in 1972. Suwa Seikosha
(now Seiko Epson
) began developing a CMOS IC chip for a Seiko quartz watch
in 1969, and began mass-production with the launch of the Seiko
Analog Quartz 38SQW watch in 1971.
The first mass-produced CMOS consumer electronic product was the Hamilton
Pulsar "Wrist Computer" digital watch, released in 1970.
Due to low power consumption, CMOS logic has been widely used for calculators
since the 1970s.
CMOS was initially slower than NMOS logic
, thus NMOS was more widely used for computers in the 1970s.
5101 (1 kb SRAM
) CMOS memory chip (1974) had an access time
of 800 ns
whereas the fastest NMOS chip at the time, the Intel 2147 (4 kb SRAM) HMOS
memory chip (1976), had an access time of 55/70 ns.
In 1978, a Hitachi
research team led by Toshiaki Masuhara introduced the twin-well Hi-CMOS process, with its HM6147 (4 kb SRAM) memory chip, manufactured with a 3 μm process
The Hitachi HM6147 chip was able to match the performance (55/70 ns access) of the Intel 2147 HMOS chip, while the HM6147 also consumed significantly less power (15 mA
) than the 2147 (110 mA). With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common semiconductor manufacturing process
for computers in the 1980s.
In the 1980s, CMOS microprocessors overtook NMOS microprocessors. NASA
spacecraft, sent to orbit Jupiter
in 1989, used the RCA 1802
CMOS microprocessor due to low power consumption.
CMOS circuits are constructed in such a way that all P-type metal–oxide–semiconductor
(PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS
transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance
between its source and drain contacts when a low gate voltage
is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.
Static CMOS inverter. Vdd
are standing for drain and source
The adjacent image shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output, therefore, registers a high voltage.
On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low resistance) state, allowing the output from drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.
In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.
Power supply pins
The power supply pins for CMOS are called VDD
, or VCC
and Ground(GND) depending on the manufacturer. VDD
are carryovers from conventional MOS circuits and stand for the drain
These do not apply directly to CMOS, since both supplies are really source supplies. VCC
and Ground are carryovers from TTL logic
and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.
An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement
of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's laws
based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.
More complex logic functions such as those involving AND
and OR gates
require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.
Shown on the right is a circuit diagram
of a NAND gate
in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss
(ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd
(voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd
(voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND
(NOT AND) logic gate.
An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage
between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.
See Logical effort
for a method of calculating delay in a CMOS circuit.
Example: NAND gate in physical layout
The physical layout
of a NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent latchup
Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication. In step 1, silicon dioxide
layers are formed initially through thermal oxidation
Note: Gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.
This example shows a NAND
logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a P-type
substrate. The polysilicon
, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.
The inputs to the NAND
(illustrated in green color) are in polysilicon. The transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The physical layout
example matches the NAND logic circuit given in the previous example.
The N device is manufactured on a P-type substrate while the P device is manufactured in an N-type
well (n-well). A P-type substrate "tap" is connected to VSS
and an N-type n-well tap is connected to VDD
to prevent latchup
Cross section of two transistors in a CMOS gate, in an N-well CMOS process
Power: switching and leakage
CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical ASIC
in a modern 90 nanometer
process, switching the output might take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from Vdd
through the load resistor and the n-type network.
Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.
Broadly classifying, power dissipation in CMOS circuits occurs because of two components, static and dynamic:
Both NMOS and PMOS transistors have a gate–source threshold voltage
, below which the current (called sub threshold
current) through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd
might have been 5 V, and Vth
for both NMOS and PMOS might have been 700 mV). A special type of the transistor used in some CMOS circuits is the native transistor
, with near zero threshold voltage
SiO2 is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130 nm technology with gate oxides of 20 Å or thinner.
Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.
If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily. Furthermore, recent studies have shown that leakage power reduces due to aging effects as a trade-off for devices to become slower. 
Charging and discharging of load capacitances
CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from VDD
to the load capacitance to charge it and then flows from the charged load capacitance (CL
) to ground during discharge. Therefore, in one complete charge/discharge cycle, a total of Q=CL
is thus transferred from VDD
to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device:
Since most gates do not operate/switch at every clock cycle
, they are often accompanied by a factor , called the activity factor. Now, the dynamic power dissipation may be re-written as
A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1.
If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.
Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from VDD
to ground, hence creating a short-circuit current
. Short-circuit power dissipation increases with rise and fall time of the transistors.
An additional form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and PMOS logic networks are partially conductive, and current flows directly from VDD to VSS. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires ameliorates this effect, but crowbar power can be a substantial part of dynamic CMOS power.
To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a Vth
of 200 mV has a significant subthreshold leakage
current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. Multi-threshold CMOS
(MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high Vth
transistors are used when switching speed is not critical, while low Vth
transistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additional leakage
component because of current tunnelling
through the extremely thin gate dielectric. Using high-κ dielectrics
instead of silicon dioxide
that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS.
Parasitic transistors that are inherent in the CMOS structure may be turned on by input signals outside the normal operating range, e.g. electrostatic discharges
or line reflections
. The resulting latch-up
may damage or destroy the CMOS device. Clamp diodes are included in CMOS circuits to deal with these signals. Manufacturers' data sheets specify the maximum permitted current that may flow through the diodes.
Examples of commercial RF CMOS chips include Intel's DECT
cordless phone, and 802.11
) chips created by Atheros
and other companies.
Commercial RF CMOS products are also used for Bluetooth
and Wireless LAN
RF CMOS is also used in the radio transceivers for wireless standards such as GSM
, Wi-Fi, and Bluetooth, transceivers for mobile networks such as 3G, and remote units in wireless sensor networks
RF CMOS technology is crucial to modern wireless communications, including wireless networks and mobile communication
devices. One of the companies that commercialized RF CMOS technology was Infineon
. Its bulk CMOS RF switches
sell over 1 billion units annually, reaching a cumulative 5 billion units, as of 2018.
Conventional CMOS devices work over a range of −55 °C to +125 °C.
There were theoretical indications as early as August 2008 that silicon CMOS will work down to −233 °C (40 K
Functioning temperatures near 40 K have since been achieved using overclocked AMD Phenom II
processors with a combination of liquid nitrogen
and liquid helium
Single-electron MOS transistors
Ultra small (L = 20 nm, W = 20 nm) MOSFETs achieve the single-electron limit when operated at cryogenic temperature over a range of −269 °C (4 K
) to about −258 °C (15 K
). The transistor displays Coulomb blockade
due to progressive charging of electrons one by one. The number of electrons confined in the channel is driven by the gate voltage, starting from an occupation of zero electrons, and it can be set to one or many.
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