Computer Architecture Lab/SS2013/Group3/Assignment2

BraveMIPS Instruction Set Architecture

BraveMIPS Instruction Set Format

The format of the 32bit MIPS I processor is kept:

Type	-31-                                 format (bits)                                 -0-
R	opcode (6)	rs (5)	rt (5)	rd (5)	shamt (5)	funct (6)
I	opcode (6)	rs (5)	rt (5)	immediate (16)
J	opcode (6)	address (26)

(same as on Wikipedia Page)

BraveMIPS Instruction Set

The instruction set is focused on integer-based instructions and it essentially consists of a subset of the MIPS Instruction Set (see the full set on Wikipedia, section "Integer"). Other instructions might be added as project progresses.

Category	Name	Instruction syntax	Meaning	Format/opcode/funct			Notes/Encoding
Arithmetic	Add	add $d,$s,$t	$d = $s + $t	R	0	2016	adds two registers, executes a trap on overflow 000000ss sssttttt ddddd--- --100000
	Subtract	sub $d,$s,$t	$d = $s - $t	R	0	2216	subtracts two registers, executes a trap on overflow 000000ss sssttttt ddddd--- --100010
	Add immediate	addi $t,$s,C	$t = $s + C (signed)	I	816	-	Used to add sign-extended constants (and also to copy one register to another: addi $1, $2, 0), executes a trap on overflow 001000ss sssttttt CCCCCCCC CCCCCCCC
	Multiply	mult $s,$t	LO = (($s * $t) << 32) >> 32; HI = ($s * $t) >> 32;	R	0	1816	Multiplies two registers and puts the 64-bit result in two special memory spots - LO and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) $s * $t . See mfhi and mflo for accessing LO and HI regs.
	Divide	div $s, $t	LO = $s / $t     HI = $s % $t	R	0	1A16	Divides two registers and puts the 32-bit integer result in LO and the remainder in HI.
Data Transfer	Load word	lw $t,C($s)	$t = Memory[$s + C]	I	2316	-	loads the word stored from: MEM[$s+C] and the following 3 bytes.
	Store word	sw $t,C($s)	Memory[$s + C] = $t	I	2B16	-	stores a word into: MEM[$s+C] and the following 3 bytes. The order of the operands is a large source of confusion.
Logical	And	and $d,$s,$t	$d = $s & $t	R	0	2416	Bitwise operation and 000000ss sssttttt ddddd--- --100100
	And immediate	andi $t,$s,C	$t = $s & C	I	C16	-	Leftmost 16 bits are padded with 0's 001100ss sssttttt CCCCCCCC CCCCCCCC
	Or	or $d,$s,$t	$d = $s | $t	R	0	2516	Bitwise or
	Or immediate	ori $t,$s,C	$t = $s | C	I	D16	-	Leftmost 16 bits are padded with 0's
	Exclusive or	xor $d,$s,$t	$d = $s ^ $t	R	0	2616
	Nor	nor $d,$s,$t	$d = ~ ($s | $t)	R	0	2716	Bitwise nor
	Set on less than	slt $d,$s,$t	$d = ($s < $t)	R	0	2A16	Tests if one register is less than another.
	Set on less than immediate	slti $t,$s,C	$t = ($s < C)	I	A16	-	Tests if one register is less than a constant.
Bitwise Shift	Shift left logical	sll $d,$t,shamt	$d = $t << shamt	R	0	0	shifts shamt number of bits to the left (multiplies by $2^{shamt}$)
	Shift right logical	srl $d,$t,shamt	$d = $t >> shamt	R	0	216	shifts shamt number of bits to the right - zeros are shifted in (divides by $2^{shamt}$). Note that this instruction only works as division of a two's complement number if the value is positive.
Conditional branch	Branch on equal	beq $s,$t,C	if ($s == $t) go to PC+4+4*C	I	416	-	Goes to the instruction at the specified address if two registers are equal. 000100ss sssttttt CCCCCCCC CCCCCCCC
	Branch on not equal	bne $s,$t,C	if ($s != $t) go to PC+4+4*C	I	516	-	Goes to the instruction at the specified address if two registers are not equal.
Unconditional jump	Jump	j C	PC = PC+4[31:28] . C*4	J	216	-	Unconditionally jumps to the instruction at the specified address.
	Jump register	jr $s	goto address $s	R	0	816	Jumps to the address contained in the specified register

BraveMIPS Assembler

The assembler is based around JFlex and CUP (Java implementations of a lexer and parser). Until now I have successfully "compiled" the lexer file, whose source is found here: /assembler/jflex/bravemips_scanner.l I still need to get the CUP-specific syntax to run and integrate the two.

NOTE: in the worst case scenario, I might implement a pure Java String manipulation-based assembler (if I will have problems with JFlex and CUP).